17.3 TLB Refill Vector Selection

Soft*1 Reset Exception

The Soft Reset exception occurs in response to a Soft Reset (See Chapter 8, the section titled "Soft Reset Sequence").

A Soft Reset exception is not maskable.

The processor differentiates between a Cold Reset and a Soft Reset as follows:

• A Cold Reset occurs when the SysGnt* signal is asserted while the SysReset* signal is also asserted.
• A Soft Reset occurs if the SysGnt* signal remains negated when a SysReset* signal is asserted.

When a Soft Reset exception occurs, the SR bit of the Status register is set, distinguishing this exception from a Cold Reset exception.

When a Soft Reset is detected, the processor initializes minimum processor state. This allows the processor to fetch and execute the instructions of the exception handler, which in turn dumps the current architectural state to external logic. Hardware state that loses architectural state is not initialized unless it is necessary to execute instructions from unmapped uncached space that reads the registers, TLB, and cache contents.

The Soft Reset can begin on an arbitrary cycle boundary and can abort multicycle operations in progress, so it may alter machine state. Hence, caches, memory, or other processor states can be inconsistent: data cache blocks may stay at the refill state and any cached loads/stores to these blocks will hang the processor. Therefore, CacheOps should be used to dump the cache contents.

After the processor state is read out, the processor should be reset with a Cold Reset sequence.

A Soft Reset exception preserves the contents of all registers, except for:

• ErrorEPC register, which contains the PC
• ERL bit of the Status register, which is set to 1
• SR bit of the Status register, which is set to 1 on Soft Reset or an NMI; 0 for a Cold Reset
• BEV bit of the Status register, which is set to 1
• TS bit of the Status register, which is set to 0
• PC is set to the reset vector 0xFFFF FFFF BFC0 0000
• clears any pending Cache Error exceptions

It is not normally possible to continue program execution after returning from this exception, since a SysReset* signal can be accepted anytime.